I. Field of the Invention
The present invention relates to the field of video signal processing, and more particularly to a video decoder debugging system and method thereof.
II. Background of the Invention
Digital video has become common in the field of consumer electronics, due in large part to the emergence of digital video standards such as MPEG-1, MPEG-2 and MPEG-4. The challenging of a video decoder technology is to design a decoder that can precisely decode the bitstream data and send to the display engine for viewing.
If an error happened during the decoding process, the video decoder will not be able to deliver a correct picture frame to the display. A debugger must find the error data path and fix the error in a short time in order to meet users' need.
In FIG. 1, a schematic diagram illustrates a conventional video decoder functional blocks that decode multimedia bitstream data.
As shown, the conventional video decoder system 100 includes a header parser 101, a bitstream buffer 102, a variable length decoder (VLD) 103, an inverse discrete Cosine transform (IDCT) 104, a motion compensation (MC) 105, an address translation and arbiter 106, a reconstruction 107 and a video decoder controller (VDEC) 108. The VDEC controller 108 issues control signals to regulate the operation of the above-mentioned functional blocks. The address translation and arbiter 106 connects to a traffic controller 120 and the traffic controller 120 further connects to a storage device 130, e.g., double data rate dynamic random access memory (DDR). The address translation and arbiter 106 also connects to the bitstream buffer 102 and the motion compensation 105. The bitstream buffer 102 connects to the header parser 101 and the variable length decoder (VLD) 103. The header parser 101 connects to the variable length decoder (VLD) 103 and the address translation and arbiter 106. The variable length decoder (VLD) 103 connects to the inverse discrete Cosine transform (IDCT) 104 and the motion compensation 105. The inverse discrete Cosine transform (IDCT) 104 and the motion compensation 105 connect to the reconstruction 107. The reconstruction 107 connects to the address translation and arbiter 106.
An encoded bitstream data is fetched from the DDR 130 via the traffic controller 120 by the address translation and arbiter 106 and put into the bitstream buffer 102. The encoded bitstream data is then sent to the header parser 101 for parsing system information and such system information is sent back to DDR 130 via the address translation and arbiter 106 for the use of CPU or VDEC controller 108. The bitstream buffer 102 sends the bitstream data to VLD 103 for parsing data information with reference to the information provided by header parser 101. VLD 103 sends the motion vector to TDCT 104 and MC 105. The TDCT 104 will generate a spatial domain difference. MC 105 will fetch a reference frame from the DDR 130 with reference to the motion vector provided by VLD 103. Both the output of IDCT 104 and MC 105 will be sent to reconstruction 107 and have a decoded frame. The traffic controller 120 further connects to a reduced instruction set computer (RISC) 140 for additional data computing, an audio decoder 150 for audio signal decoding and a display engine 160 for displaying the decoded video bitstream data.
However, it is difficult to locate the error data path during the decoding process because: (1) The debugger needs to dump the decoded frame buffer, which is a huge size of data, from the external DRAM to compare with the golden data, and (2) the debugger needs to rely on the logic analyzer to trace all the possible signals which cost a lot of time and equipments.
Therefore, there is a need for an alternative video decoder structure featuring a debugging functional block design that can improve the above-mentioned drawbacks.